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STB70NH03L
N-channel 60V - 0.0075 - 70A - D2PAK STripFETTM III Power MOSFET for DC-DC conversion
General features
Type STB70NH03L

VDSS 30V
RDS(on) < 0.009
ID 60A (1)
RDS(on) x Qg industry benchmark Conduction losses reduced
1 3
Switching losses reduced Low threshold device
DPAK
Description
The device utilizes the latest advanced design rules of ST's proprietary STripFETTM technology. It is ideal in high performance DC-DC converter applications where efficiency is to be achieved at very high output currents.
Internal schematic diagram
Applications
Switching application
Order codes
Part number STB70NH03LT4 Marking B70NH03L Package DPAK Packaging Tape & reel
July 2006
Rev 6
1/15
www.st.com 15
Contents
STB70NH03L
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................ 6
3 4 5 6 7
Test circuit
................................................ 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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STB70NH03L
Electrical ratings
1
Electrical ratings
Table 1.
Symbol VDS VDGR VGS ID (1) ID
(1) (2)
Absolute maximum ratings
Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Value 30 30 20 60 43 240 858 Unit V V V A A A W W/C 300 -55 to 175 Operating Junction Temperature mJ C
IDM
PTOT
(3)
EAS
Single Pulse Avalanche Energy Storage Temperature
Tstg TJ
1. Value limited by wire bonding 2. Pulse width limited by safe operting area 3. Starting TJ = 25 oC, ID = 30A, VDD = 20V
Table 2.
Symbol RthJC RthJA Tl
Thermal data
Parameter Thermal resistance junction-case max Thermal resistance junction-ambient max Maximum lead temperature for soldering purpose Value 1.87 62.5 300 Unit C/W C/W C
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Electrical characteristics
STB70NH03L
2
Electrical characteristics
(TCASE = 25C unless otherwise specified) Table 3.
Symbol V(BR)DSS
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage Drain current (VGS = 0) Gate-body leakage Current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 A, VGS = 0 VDS = max rating VDS = max rating TC = 125C VGS = 20 V VDS = VGS VGS = 10 V VGS = 5 V ID = 250 A ID = 30 A ID = 30 A 1 0.0075 0.0095 0.0135 0.009 Min 30 1 10 100 Typ Max Unit V A A nA V
IDSS
IGSS VGS(th) RDS(on)
Table 4.
Symbol gfs (1) Ciss Coss Crss
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Gate Input Resistance Turn-on delay time Rise time Turn-off delay Time Fall time Total gate charge Gate-source charge Gate-drain charge Third-quadrant gate charge Test conditions VDS = 10 V ID = 18 A Min Typ 25 2200 380 49 Max Unit S pF pF pF
VDS = 10V f = 1 MHz VGS = 0
RG td(on) tr td(off) tf Qg Qgs Qgd Qgls(2)
f = 1 MHz gate DC bias = 0 test signal level = 20 mV open drain
1.5 21 95 19 15 15.7 8.3 3.4 15 21
VDD = 15 V RG = 4.7
ID = 30 A VGS = 5 V
ns ns
VDD= 15V ID= 70A VGS= 5V VDS< 0 V VGS= 10 V
nC nC nC nC
1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 % 2. Gate charge for synchronous operation . See Chapter 6: Appendix A
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STB70NH03L
Electrical characteristics
Table 5.
Symbol ISD ISDM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage ISD = 30 A VGS = 0 32 51 3.2 Test conditions Min Typ Max 60 240 1.3 Unit A A V ns nC A
(1)
VSD(2) trr Qrr IRRM
Reverse recovery time I = 60 A di/dt = 100A/s Reverse recovery charge SD TJ = 150C VDD = 20 V Reverse recovery current
1. Pulse width limited by safe operating area 2. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %
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Electrical characteristics
STB70NH03L
2.1
Figure 1.
Electrical characteristics (curves)
Safe operating area Figure 2. Thermal impedance
Figure 3.
Output characterisics
Figure 4.
Transfer characteristics
Figure 5.
Transconductance
Figure 6.
Static drain-source on resistance
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STB70NH03L Figure 7. Gate charge vs gate-source voltage Figure 8.
Electrical characteristics Capacitance variations
Figure 9.
Normalized gate threshold voltage vs temperature
Figure 10. Normalized on resistance vs temperature
Figure 11. Source-drain diode forward characteristics
Figure 12. Normalized Breakdown vs temperature
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Test circuit
STB70NH03L
3
Test circuit
Figure 14. Gate charge test circuit
Figure 13. Switching times test circuit for resistive load
Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit
Figure 17. Unclamped inductive waveform
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STB70NH03L
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
STB70NH03L
D2PAK MECHANICAL DATA TO-247 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 B B2 C C2 D D1 E E1 G L L2 L3 M R V2 0 4.88 15 1.27 1.4 2.4 0.4 4 10 8.5 5.28 15.85 1.4 1.75 3.2 0.192 0.590 0.050 0.055 0.094 0.015 4.4 2.49 0.03 0.7 1.14 0.45 1.23 8.95 8 10.4 0.393 0.334 0.208 0.625 0.055 0.068 0.126 TYP MAX. 4.6 2.69 0.23 0.93 1.7 0.6 1.36 9.35 MIN. 0.173 0.098 0.001 0.027 0.044 0.017 0.048 0.352 0.315 TYP. MAX. 0.181 0.106 0.009 0.036 0.067 0.023 0.053 0.368 inch
3
1
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STB70NH03L
Packaging mechanical data
5
Packaging mechanical data
D2PAK FOOTPRINT
TAPE AND REEL SHIPMENT
REEL MECHANICAL DATA
DIM. A B C D G N T 1.5 12.8 20.2 24.4 100 30.4 26.4 13.2 mm MIN. MAX. 330 0.059 0.504 0.520 0795 0.960 1.039 3.937 1.197 BULK QTY 1000 inch MIN. MAX. 12.992
TAPE MECHANICAL DATA
DIM. A0 B0 D D1 E F K0 P0 P1 P2 R T W mm MIN. 10.5 15.7 1.5 1.59 1.65 11.4 4.8 3.9 11.9 1.9 50 0.25 23.7 24.3 MAX. 10.7 15.9 1.6 1.61 1.85 11.6 5.0 4.1 12.1 2.1 inch MIN. MAX. 0.413 0.421 0.618 0.626 0.059 0.063 0.062 0.063 0.065 0.073 0.449 0.456 0.189 0.197 0.153 0.161 0.468 0.476 0.075 0.082 1.574 0.35 0.0098 0.0137 0.933 0.956
BASE QTY 1000
* on sales type
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Appendix A
STB70NH03L
6
Appendix A
Figure 18. Buck converter: power losses estimation
The power losses associated with the FETs in a synchronous buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature.

The low side (SW2) device requires: Very low RDS(on) to reduce conduction losses Small Qgls to reduce the gate charge losses Small Coss to reduce losses due to output capacitance Small Qrr to reduce losses on SW1 during its turn-on The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon; The high side (SW1) device requires: Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate Small Qg to have a faster commutation and to reduce gate charge losses Low RDS(on) to reduce the conduction losses.
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STB70NH03L
Appendix A
Table 6.
Power losses calculation
High side switching (SW1) Low side switch (SW2)
Pconduction
R DS(on)SW1 * I 2 * L
R DS(on)SW2 * I 2 * (1 - ) L
IL Ig
Pswitching
Vin * (Q gsth(SW1) + Q gd(SW1) ) * f *
Zero Voltage Switching
Recovery
(1)
Not applicable
Vin * Q rr(SW2) * f
Pdiode Conductio n Not applicable
Vf(SW2) * I L * t deadtime * f Q gls(SW2) * Vgg * f
Vin * Q oss(SW2) * f 2
Pgate(QG)
Q g(SW1) * Vgg * f
PQoss
Vin * Q oss(SW1) * f 2
1. Dissipated by SW1 during turn-on
Table 7.
Paramiters meaning
Meaning Duty-cycle Post threshold gate charge Third quadrant gate charge On state losses On-off transition losses Conduction and reverse recovery diode losses Gate drive losses Output capacitance losses
Parameter d Qgsth Qgls Pconduction Pswitching Pdiode Pgate PQoss
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Revision history
STB70NH03L
7
Revision history
Table 8.
Date 21-Jun-2004 20-Jul-2006
Revision history
Revision 5 6 Complete document New template, no content change Changes
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STB70NH03L
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